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 74VCX16374 Low-Voltage 1.8/2.5/3.3V 16-Bit D-Type Flip-Flop
With 3.6 V-Tolerant Inputs and Outputs (3-State, Non-Inverting)
The 74VCX16374 is an advanced performance, non-inverting 16-bit D-type flip-flop. It is designed for very high-speed, very low-power operation in 1.8 V, 2.5 V or 3.3 V systems. The VCX16374 is byte controlled, with each byte functioning identically, but independently. Each byte has separate Output Enable and Clock Pulse inputs. These control pins can be tied together for a full 16-bit operation. When operating at 2.5 V (or 1.8 V) the part is designed to tolerate voltages it may encounter on either inputs or outputs when interfacing to 3.3 V busses. It is guaranteed to be overvoltage tolerant to 3.6 V. The 74VCX16374 consists of 16 edge-triggered flip-flops with individual D-type inputs and 3.6 V-tolerant 3-state outputs. The clocks (CPn) and Output Enables (OEn) are common to all flip-flops within the respective byte. The flip-flops will store the state of individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CP) transition. With the OE LOW, the contents of the flip-flops are available at the outputs. When the OE is HIGH, the outputs go to the high impedance state. The OE input level does not affect the operation of the flip-flops.
Features http://onsemi.com MARKING DIAGRAM
48
48 1
VCX16374 AWLYYWW
TSSOP-48 DT SUFFIX CASE 1201
1 = Assembly Location = Wafer Lot = Year = Work Week
A WL YY WW
PIN NAMES
Pins OEn CPn D0-D15 O0-O15 Function Output Enable Inputs Clock Pulse Inputs Inputs Outputs
* Designed for Low Voltage Operation: VCC = 1.65 V - 3.6 V * 3.6 V Tolerant Inputs and Outputs * High Speed Operation: 3.0 ns max for 3.0 V to 3.6 V * * * * * * *
3.9 ns max for 2.3 V to 2.7 V 7.8 ns max for 1.65 V to 1.95 V Static Drive: 24 mA Drive at 3.0 V 18 mA Drive at 2.3 V 6 mA Drive at 1.65 V Supports Live Insertion and Withdrawal IOFF Specification Guarantees High Impedance When VCC = 0 V Near Zero Static Supply Current in All Three Logic States (20 mA) Substantially Reduces System Power Requirements Latchup Performance Exceeds 250 mA @ 125C ESD Performance: Human Body Model >2000 V Machine Model >200 V All Devices in Package TSSOP are Inherently Pb-Free*
ORDERING INFORMATION
Device 74VCX16374DT 74VCX16374DTR Package TSSOP (Pb-Free) TSSOP (Pb-Free) Shipping 39 / Rail 2500 / Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2004
1
November, 2004 - Rev. 5
Publication Order Number: 74VCX16374/D
74VCX16374
OE1 1 O0 2 O1 3 GND 4 O2 5 O3 6 VCC 7 O4 8 O5 9 GND 10 O6 11 O7 12 O8 13 O9 14 GND 15 O10 16 O11 17 VCC 18 O12 19 O13 20 GND 21 O14 22 O15 23 OE2 24 48 CP1 47 D0 46 D1 45 GND 44 D2 43 D3 42 VCC 41 D4 40 D5 39 GND 38 D6 37 D7 36 D8 35 D9 34 GND 33 D10 32 D11 31 VCC 30 D12 29 D13 28 GND 27 D14 26 D15 25 CP2 D7 37 D6 38 D5 40 D4 41 D3 43 nCP D nCP D nCP D nCP D nCP D Q D2 44 nCP D Q 5 O2 D10 33 nCP D nCP D nCP D nCP D nCP D nCP D Q 16 O10 D1 D0 OE1 CP1 1 48 47 nCP D nCP D Q 2 O0 OE2 CP2 D8 24 25 36 nCP D nCP D Q 13 O8
46
Q
3
O1
D9
35
Q
14
O9
6
O3
D11
32
Q
17
O11
Q
8
O4
D12
30
Q
19
O12
Q
9
O5
D13
29
Q
20
O13
Q
11
O6
D14
27
Q
22
O14
Q
12
O7
D15
26
Q
23
O15
Figure 1. 48-Lead Pinout (Top View)
Figure 2. Logic Diagram
OE1 48 CP1 25 CP2 24 OE2 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26
1
EN1 EN2 EN3 EN4
1
1 2
1
1
3
1
4
2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23
O0 O1 O2 O3 O4 O5 O6 O7 O8 O9 O10 O11 O12 O13 O14 O15
Figure 3. IEC Logic Diagram
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74VCX16374
TRUTH TABLE
Inputs CP1 X X OE1 L L L H D0:7 H L X X Outputs O0:7 H L O0 Z CP2 X X Inputs OE2 L L L H D8:15 H L X X Outputs O8:15 H L O0 Z
H = High Voltage Level L = Low Voltage Level Z = High Impedance State = Low-to-High Transition X = High or Low Voltage Level and Transitions Are Acceptable, for I CC reasons, DO NOT FLOAT Inputs O0 = No Change
ABSOLUTE MAXIMUM RATINGS
Symbol VCC VI VO Parameter DC Supply Voltage DC Input Voltage DC Output Voltage Value -0.5 to +4.6 -0.5 VI +4.6 -0.5 VO +4.6 -0.5 VO VCC + 0.5 IIK IOK DC Input Diode Current DC Output Diode Current -50 -50 +50 IO ICC IGND TSTG DC Output Source/Sink Current DC Supply Current Per Supply Pin DC Ground Current Per Ground Pin Storage Temperature Range 50 100 100 -65 to +150 Output in 3-State Note 1; Outputs Active VI < GND VO < GND VO > VCC Condition Unit V V V V mA mA mA mA mA mA C
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. IO absolute maximum rating must be observed.
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VI VO IOH IOL IOH IOL IOH IOL TA Dt/DV Supply Voltage Input Voltage Output Voltage HIGH Level Output Current, VCC = 3.0 V - 3.6 V LOW Level Output Current, VCC = 3.0 V - 3.6 V HIGH Level Output Current, VCC = 2.3 V - 2.7 V LOW Level Output Current, VCC = 2.3 V - 2.7 V HIGH Level Output Current, VCC = 1.65 V - 1.95 V LOW Level Output Current, VCC = 1.65 V - 1.95 V Operating Free-Air Temperature Input Transition Rise or Fall Rate, VIN from 0.8 V to 2.0 V, VCC = 3.0 V -40 0 (Active State) (3-State) Parameter Operating Data Retention Only Min 1.65 1.2 -0.3 0 0 Typ 3.3 3.3 Max 3.6 3.6 3.6 VCC 3.6 -24 24 -18 18 -6 6 +85 10 Unit V V V mA mA mA mA mA mA C ns/V
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74VCX16374
DC ELECTRICAL CHARACTERISTICS
TA = -40C to +85C Symbol VIH Characteristic HIGH Level Input Voltage (Note 2) Condition 1.65 V VCC < 2.3 V 2.3 V VCC 2.7 V 2.7 V < VCC 3.6 V VIL LOW Level Input Voltage (Note 2) 1.65 V VCC < 2.3 V 2.3 V VCC 2.7 V 2.7 V < VCC 3.6 V VOH HIGH Level Output Voltage 1.65 V VCC 3.6 V; IOH = -100 mA VCC = 1.65 V; IOH = -6 mA VCC = 2.3 V; IOH = -6 mA VCC = 2.3 V; IOH = -12 mA VCC = 2.3 V; IOH = -18 mA VCC = 2.7 V; IOH = -12 mA VCC = 3.0 V; IOH = -18 mA VCC = 3.0 V; IOH = -24 mA VOL LOW Level Output Voltage 1.65 V VCC 3.6 V; IOL = 100 mA VCC = 1.65 V; IOL = 6 mA VCC = 2.3 V; IOL = 12 mA VCC = 2.3 V; IOL = 18 mA VCC = 2.7 V; IOL = 12 mA VCC = 3.0 V; IOL = 18 mA VCC = 3.0 V; IOL = 24 mA II IOZ IOFF ICC Input Leakage Current 3-State Output Current Power-Off Leakage Current Quiescent Supply Current (Note 3) 1.65 V VCC 3.6 V; 0 V VI 3.6 V 1.65 V VCC 3.6 V; 0 V VO 3.6 V; VI = VIH or VIL VCC = 0 V; VI or VO = 3.6 V 1.65 V VCC 3.6 V; VI = GND or VCC 1.65 V VCC 3.6 V; 3.6 V VI, VO 3.6 V DICC Increase in ICC per Input 2.7 V < VCC 3.6 V; VIH = VCC - 0.6 V VCC - 0.2 1.25 2.0 1.8 1.7 2.2 2.4 2.2 0.2 0.3 0.4 0.6 0.4 0.4 0.55 5.0 10 10 20 20 750 mA mA mA mA mA mA V Min 0.65 x VCC 1.6 2.0 0.35 x VCC 0.7 0.8 V V Max Unit V
2. These values of VI are used to test DC electrical characteristics only. 3. Outputs disabled or 3-state only.
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74VCX16374
AC CHARACTERISTICS (Note 4; tR = tF = 2.0 ns; CL = 30 pF; RL = 500 W)
TA = -40C to +85C VCC = 3.0 V to 3.6 V Symbol fmax tPLH tPHL tPZH tPZL tPHZ tPLZ ts th tw tOSHL tOSLH Parameter Clock Pulse Frequency Propagation Delay CP-to-On Output Enable Time to High and Low Level Output Disable Time From High and Low Level Setup Time, High or Low Dn-to-CP Hold Time, High or Low Dn-to-CP CP Pulse Width, High Output-to-Output Skew (Note 5) Waveform 1 1 2 2 3 3 3 Min 250 0.8 0.8 0.8 0.8 0.8 0.8 1.5 1.0 1.5 0.5 0.5 3.0 3.0 3.5 3.5 3.5 3.5 Max VCC = 2.3 V to 2.7 V Min 200 1.0 1.0 1.0 1.0 1.0 1.0 1.5 1.0 1.5 0.5 0.5 3.9 3.9 4.6 4.6 3.8 3.8 Max VCC = 1.65 V to 1.95 V Min 100 1.5 1.5 1.5 1.5 1.5 1.5 2.5 1.0 4.0 0.75 0.75 7.8 7.8 9.2 9.2 6.8 6.8 Max Unit MHz ns ns ns ns ns ns ns
4. For CL = 50 pF, add approximately 300 ps to the AC maximum specification. 5. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH); parameter guaranteed by design.
AC CHARACTERISTICS (tR = tF = 2.0 ns; CL = 50 pF; RL = 500 W)
TA = -40C to +85C VCC = 3.0 V to 3.6 V Symbol fmax tPLH tPHL tPZH tPZL tPHZ tPLZ tOSHL tOSLH Parameter Clock Pulse Frequency Propagation Delay CP-to-On Output Enable Time to High and Low Level Output Disable Time From High and Low Level Output-to-Output Skew (Note 6) Waveform 4 4 5 5 Min 150 1.0 1.0 1.0 1.0 1.0 1.0 4.2 4.2 4.8 4.8 4.3 4.3 0.5 0.5 Max VCC = 2.7 V Min 150 4.9 4.9 5.9 5.9 4.7 4.7 0.5 0.5 Max Unit MHz ns ns ns ns
6. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH); parameter guaranteed by design.
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74VCX16374
DYNAMIC SWITCHING CHARACTERISTICS
TA = +25C Symbol VOLP Characteristic Dynamic LOW Peak Voltage y g (Note (N t 7) Condition VCC = 1.8 V, CL = 30 pF, VIH = VCC, VIL = 0 V VCC = 2.5 V, CL = 30 pF, VIH = VCC, VIL = 0 V VCC = 3.3 V, CL = 30 pF, VIH = VCC, VIL = 0 V VOLV Dynamic LOW Valley Voltage y y g (Note 7) VCC = 1.8 V, CL = 30 pF, VIH = VCC, VIL = 0 V VCC = 2.5 V, CL = 30 pF, VIH = VCC, VIL = 0 V VCC = 3.3 V, CL = 30 pF, VIH = VCC, VIL = 0 V VOHV Dynamic HIGH Valley Voltage y y g (Note 8) VCC = 1.8 V, CL = 30 pF, VIH = VCC, VIL = 0 V VCC = 2.5 V, CL = 30 pF, VIH = VCC, VIL = 0 V VCC = 3.3 V, CL = 30 pF, VIH = VCC, VIL = 0 V Typ 0.25 0.6 0.8 -0.25 -0.6 -0.8 1.5 1.9 2.2 V V Unit V
7. Number of outputs defined as "n". Measured with "n-1" outputs switching from HIGH-to-LOW or LOW-to-HIGH. The remaining output is measured in the LOW state. 8. Number of outputs defined as "n". Measured with "n-1" outputs switching from HIGH-to-LOW or LOW-to-HIGH. The remaining output is measured in the HIGH state.
CAPACITIVE CHARACTERISTICS
Symbol CIN COUT CPD Parameter Input Capacitance Output Capacitance Power Dissipation Capacitance Condition Note 9 Note 9 Note 9, 10 MHz Typical 6 7 20 Unit pF pF pF
9. VCC = 1.8 V, 2.5 V or 3.3 V; VI = 0 V or VCC.
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74VCX16374
VIH Dn ts CPn Vm fmax tPLH, tPHL On Vm VOL WAVEFORM 1 - PROPAGATION DELAYS, SETUP AND HOLD TIMES tR = tF = 2.0 ns, 10% to 90%; f = 1 MHz; tW = 500 ns Vm th Vm 0V tPZL VOH Vm Vx VOL WAVEFORM 2 - OUTPUT ENABLE AND DISABLE TIMES tR = tF = 2.0 ns, 10% to 90%; f = 1 MHz; tW = 500 ns tPLZ Vm 0V VIH On VIH OEn tPZH Vm Vm tPHZ Vm 0V VOH Vy 0V VCC
On
Figure 4. AC Waveforms
VIH CPn Vm tw Vm 0V VIH Vm 0V WAVEFORM 3 - PULSE WIDTH tR = tF = 2.0 ns (or fast as required) from 10% to 90%
tw CPn Vm
Figure 5. AC Waveforms
Table 1. AC WAVEFORMS
VCC Symbol VIH Vm Vx Vy 3.3 V 0.3 V 2.7 V 1.5 V VOL + 0.3 V VOH - 0.3 V 2.5 V 0.2 V VCC VCC/2 VOL + 0.15 V VOH - 0.15 V 1.8 V 0.15 V VCC VCC/2 VOL + 0.15 V VOH - 0.15 V
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74VCX16374
VCC 6 V or VCC x 2 OPEN GND
PULSE GENERATOR RT
RL DUT CL RL
Figure 6. Test Circuit
Table 2. TEST CIRCUIT
TEST tPLH, tPHL tPZL, tPLZ tPZH, tPHZ Open 6 V at VCC = 3.3 0.3 V; VCC x 2 at VCC = 2.5 0.2 V; 1.8 0.15 V GND SWITCH
CL = 30 pF or equivalent (Includes jig and probe capacitance) RL = 500 W or equivalent RT = ZOUT of pulse generator (typically 50 W)
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74VCX16374
VIH Dn Vm ts CPn Vm fmax tPLH, tPHL On Vm VOL WAVEFORM 4 - PROPAGATION DELAYS, SETUP AND HOLD TIMES tR = tF = 2.0 ns, 10% to 90%; f = 1 MHz; tW = 500 ns th Vm 0V tPZL VOH Vm Vx VOL WAVEFORM 5 - OUTPUT ENABLE AND DISABLE TIMES tR = tF = 2.0 ns, 10% to 90%; f = 1 MHz; tW = 500 ns tPLZ Vm 0V VIH On VIH OEn tPZH Vm Vm tPHZ Vm 0V VOH Vy 0V VCC
On
Figure 7. AC Waveforms
VIH Vm CPn tw Vm 0V VIH CPn Vm 0V WAVEFORM 6 - PULSE WIDTH tR = tF = 2.0 ns (or fast as required) from 10% to 90%
tw Vm
Figure 8. AC Waveforms
Table 3. AC WAVEFORMS
VCC Symbol VIH Vm Vx Vy 3.3 V 0.3 V 2.7 V 1.5 V VOL + 0.3 V VOH - 0.3 V 2.7 V 2.7 V 1.5 V VOL + 0.3 V VOH - 0.3 V
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74VCX16374
VCC 6 V or VCC x 2 OPEN GND
PULSE GENERATOR RT
RL DUT CL RL
Figure 9. Test Circuit
Table 4. TEST CIRCUIT
TEST tPLH, tPHL tPZL, tPLZ tPZH, tPHZ Open 6 V at VCC = 3.3 0.3 V; VCC x 2 at VCC = 2.5 0.2 V; 1.8 0.15 V GND SWITCH
CL = 50 pF or equivalent (Includes jig and probe capacitance) RL = 500 W or equivalent RT = ZOUT of pulse generator (typically 50W)
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74VCX16374
PACKAGE DIMENSIONS
TSSOP DT SUFFIX CASE 1201-01 ISSUE A
48X
K REF 0.12 (0.005)
M
J J1
48 25
M
SECTION N-N L B -U- N
1 24
0.254 (0.010)
PIN 1 IDENT.
A -V-
N F DETAIL E M 0.25 (0.010)
D 0.076 (0.003) -T- SEATING
PLANE
C DETAIL E G H
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CCC EEE CCC EEE CCC
TU
S
V
S
K K1
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 5. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 6. DIMENSIONS A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 12.40 12.60 6.00 6.20 --- 1.10 0.05 0.15 0.50 0.75 0.50 BSC 0.37 --- 0.09 0.20 0.09 0.16 0.17 0.27 0.17 0.23 7.95 8.25 0_ 8_ INCHES MIN MAX 0.488 0.496 0.236 0.244 --- 0.043 0.002 0.006 0.020 0.030 0.0197 BSC 0.015 --- 0.004 0.008 0.004 0.006 0.007 0.011 0.007 0.009 0.313 0.325 0_ 8_
TU
S
-W-
74VCX16374
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 61312, Phoenix, Arizona 85082-1312 USA Phone: 480-829-7710 or 800-344-3860 Toll Free USA/Canada Fax: 480-829-7709 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051 Phone: 81-3-5773-3850 ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative.
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74VCX16374/D
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